Personal tools



Jump to: navigation, search

Title FP7 Centre of Research Excellence in Dependable Embedded Systems - CREDES
PI Valery Sklyarov
Participants Iouliia Skliarova
Funded by EU FP7
Global funding (€) N/Awarning.png"N/A" is not a number.
RU funding (€) Travels Aveiro/Tallinnwarning.png"Travels Aveiro/Tallinn" is not a number.
Starts 2009/09/01
Ends 2012/02/28

FP7 Centre of Research Excellence in Dependable Embedded Systems - CREDES Summary: The overall aim of the CREDES project is to create a Centre of Research Excellence in Dependable Embedded Systems, based on the research potential of Department of Computer Engineering and Department of Computer Science and infrastructure of the Laboratory for Synthesis and Analysis of Embedded Systems (ASSA) at Tallinn University of Technology. The ambition is for the Centre of Research Excellence to become one of the Europe's leading institutions responsible for R&D in the areas of design, verification, test and diagnosis of embedded systems.

The Centre of Research Excellence will be created by developing TUT's existing scientific expertise and capacities and collaborating closely with specialist research groups at University of Verona, TU Darmstadt, Brandenburg TU Cottbus, University of York, Göpel Electronic GmbH and University of Aveiro.

Although digital hardware exhibited a very high level of reliability in the past, future nanometre-scale hardware devices will become a source of problems. In nanometre IC technologies, the fault-free production of ICs will be close to impossible. Furthermore, error-free operation in the field of applications becomes uncertain since radiation and electromagnetic coupling can severely harm the function of nanometre circuits.

The main objective of the proposed centre is to develop highly innovative design and test methods and circuit architectures for embedded systems that yield reliable systems based on not reliable basic circuits. The advanced functions required include both compensation of transient hardware faults and repair mechanisms for permanent faults, based on efficient provision and administration of redundancy. Fault detection, error handling and repair (after production, but optionally also in the field) for logic devices and for interconnects are the key functions to be developed, far beyond the capabilities of today's circuits and architectures. The International Technology Roadmap for Semiconductors (ITRS) reflects these tendencies and labels built-in repair functions for logic a must from 2010, with no solutions known yet. The long-term answer to these problems at the earliest possible point of time will be crucial to the competitiveness of European industries at-large[1].

The ITRS also estimates that 70% of the systems design cycle will be spent on verification and test activities, and predicts that this share will increase. Enhancing productivity and reliability of the system verification flow is thus a key competitive aspect, both in terms of time to market and end-product quality. New, hierarchical approaches for fault simulation, test generation and verification are needed to cope with the growing complexity and high quality requirements of modern embedded systems.